D12320VF25IV Datasheet, PDF (249/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
Section 7 DMA Controller
(Not Supported in the H8S/2321)
7.1 Overview
The chip has a built-in DMA controller* (DMAC) which can carry out data transfer on up to 4
channels.
Note: * The DMAC is not supported in the H8S/2321.
7.1.1 Features
The features of the DMAC are listed below.
• Choice of short address mode or full address mode
Short address mode
⎯ Maximum of 4 channels can be used
⎯ Choice of dual address mode or single address mode
⎯ In dual address mode, one of the two addresses, transfer source and transfer destination, is
specified as 24 bits and the other as 16 bits
⎯ In single address mode, transfer source or transfer destination address only is specified as
24 bits
⎯ In single address mode, transfer can be performed in one bus cycle
⎯ Choice of sequential mode, idle mode, or repeat mode for dual address mode and single
address mode
Full address mode
⎯ Maximum of 2 channels can be used
⎯ Transfer source and transfer destination address specified as 24 bits
⎯ Choice of normal mode or block transfer mode
• 16-Mbyte address space can be specified directly
• Byte or word can be set as the transfer unit
• Activation sources: internal interrupt, external request, auto-request (depending on transfer
mode)
⎯ Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts
⎯ Serial communication interface (SCI0, SCI1) transmission data empty interrupt, reception
data full interrupt
⎯ A/D converter conversion end interrupt
Rev.6.00 Sep. 27, 2007 Page 217 of 1268
REJ09B0220-0600