D12320VF25IV Datasheet, PDF (25/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

15.3 Operation........................................................................................................................... 678
15.3.1 Overview.............................................................................................................. 678
15.3.2 Pin Connections ................................................................................................... 678
15.3.3 Data Format ......................................................................................................... 680
15.3.4 Register Settings .................................................................................................. 682
15.3.5 Clock.................................................................................................................... 684
15.3.6 Data Transfer Operations ..................................................................................... 686
15.3.7 Operation in GSM Mode ..................................................................................... 694
15.3.8 Operation in Block Transfer Mode ...................................................................... 695
15.4 Usage Notes ...................................................................................................................... 696
Section 16 A/D Converter (8 Analog Input Channel Version)..........................701
16.1 Overview........................................................................................................................... 701
16.1.1 Features................................................................................................................ 701
16.1.2 Block Diagram ..................................................................................................... 702
16.1.3 Pin Configuration................................................................................................. 703
16.1.4 Register Configuration......................................................................................... 704
16.2 Register Descriptions ........................................................................................................ 705
16.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 705
16.2.2 A/D Control/Status Register (ADCSR) ............................................................... 706
16.2.3 A/D Control Register (ADCR) ............................................................................ 708
16.2.4 Module Stop Control Register (MSTPCR) .......................................................... 709
16.3 Interface to Bus Master ..................................................................................................... 710
16.4 Operation........................................................................................................................... 711
16.4.1 Single Mode (SCAN = 0) .................................................................................... 711
16.4.2 Scan Mode (SCAN = 1) ....................................................................................... 713
16.4.3 Input Sampling and A/D Conversion Time.......................................................... 715
16.4.4 External Trigger Input Timing ............................................................................. 716
16.5 Interrupts ........................................................................................................................... 717
16.6 Usage Notes ...................................................................................................................... 718
Section 17 D/A Converter..................................................................................723
17.1 Overview........................................................................................................................... 723
17.1.1 Features................................................................................................................ 723
17.1.2 Block Diagram ..................................................................................................... 724
17.1.3 Pin Configuration................................................................................................. 725
17.1.4 Register Configuration......................................................................................... 725
17.2 Register Descriptions ........................................................................................................ 726
17.2.1 D/A Data Registers 0, 1 (DADR0, DADR1) ....................................................... 726
17.2.2 D/A Control Registers 01 (DACR01) .................................................................. 726
Rev.6.00 Sep. 27, 2007 Page xxiii of xxx
REJ09B0220-0600