D12320VF25IV Datasheet, PDF (178/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.1.3 Pin Configuration
Table 6.1 summarizes the pins of the bus controller.
Table 6.1 Bus Controller Pins
Name
Address strobe
Read
High write/write enable
Low write
Chip select 0
Chip select 1
Chip select 2/row address
strobe 2
Chip select 3/row address
strobe 3
Chip select 4/row address
strobe 4
Chip select 5/row address
strobe 5
Symbol
AS
RD
HWR
LWR
CS0
CS1
CS2
CS3
CS4
CS5
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Function
Strobe signal indicating that address output
on address bus is enabled.
Strobe signal indicating that external space
is being read.
Strobe signal indicating that external space
is to be written, and upper half (D15 to D8) of
data bus is enabled.
2-CAS DRAM write enable signal^*.
Strobe signal indicating that external space
is to be written, and lower half (D7 to D0) of
data bus is enabled.
Strobe signal indicating that area 0 is
selected.
Strobe signal indicating that area 1 is
selected.
Strobe signal indicating that area 2 is
selected.
DRAM row address strobe signal when
area 2 is in DRAM space^*.
Strobe signal indicating that area 3 is
selected.
DRAM row address strobe signal when
area 3 is in DRAM space^*.
Strobe signal indicating that area 4 is
selected.
DRAM row address strobe signal when
area 4 is in DRAM space^*.
Strobe signal indicating that area 5 is
selected.
DRAM row address strobe signal when
area 5 is in DRAM space^*.
Rev.6.00 Sep. 27, 2007 Page 146 of 1268
REJ09B0220-0600