D12320VF25IV Datasheet, PDF (331/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7.13.
During burst transfer, or when one block is being transferred in block transfer, the channel will not
be changed until the end of the transfer.
Figure 7.35 shows a transfer example in which transfer requests are issued simultaneously for
channels 0A, 0B, and 1.
φ
Address bus
RD
DMA read DMA write
DMA read DMA write
DMA
DMA read DMA write read
HWR
LWR
DMA control Idle Read Write
Idle Read Write
Idle Read Write
Read
Channel 0A Request clear
Channel 0B
Channel 1
Bus
release
Request
hold
Request
hold
Selection
Non-
selection
Request clear
Request
hold
Selection ^{Request clear}
Channel 0A
transfer
Bus
release
Channel 0B
transfer
Bus
release
Channel 1 transfer
Figure 7.35 Example of Multi-Channel Transfer
Rev.6.00 Sep. 27, 2007 Page 299 of 1268
REJ09B0220-0600