D12320VF25IV Datasheet, PDF (60/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 1 Overview
Type
Bus control
DMA controller
(DMAC) ^*3
16-bit timer
pulse unit
(TPU)
Symbol
CAS^*4
LCAS^*4
WAIT
DREQ1,
DREQ0
TEND1,
TEND0
DACK1,
DACK0
TCLKD to
TCLKA
TIOCA0,
TIOCB0,
TIOCC0,
TIOCD0
TIOCA1,
TIOCB1
TIOCA2,
TIOCB2
TIOCA3,
TIOCB3,
TIOCC3,
TIOCD3
Pin No.
TFP-120 FP-128B I/O Name and Function
116
126
Output Upper column address strobe/
column address strobe: The 2-CAS
type DRAM upper column address
strobe signal.
86
94
Output Lower column address strobe: The
2-CAS type DRAM lower column
address strobe signal.
86, 92
94, 102
Input
Wait: Requests insertion of a wait
state in the bus cycle when
accessing external 3-state access
space.
62, 60
70, 66
Input DMA request 1 and 0: These pins
request DMAC activation.
63, 61
71, 69
Output DMA transfer end 1 and 0: These
pins indicate the end of DMAC data
transfer.
111, 112 121, 122 Output DMA transfer acknowledge 1 and
0: These are the DMAC single
address transfer acknowledge pins.
105, 107, 115, 117, Input Clock input D to A: These pins input
109, 110 119, 120
an external clock.
112 to 122 to I/O
109
119
108, 107 118, 117 I/O
106, 105 116, 115 I/O
71 to 68 79 to 76 I/O
Input capture/output compare
match A0 to D0: The TGR0A to
TGR0D input capture input or output
compare output, or PWM output pins.
Input capture/output compare
match A1 and B1: The TGR1A and
TGR1B input capture input or output
compare output, or PWM output pins.
Input capture/output compare
match A2 and B2: The TGR2A and
TGR2B input capture input or output
compare output, or PWM output pins.
Input capture/output compare
match A3 to D3: The TGR3A to
TGR3D input capture input or output
compare output, or PWM output pins.
Rev.6.00 Sep. 27, 2007 Page 28 of 1268
REJ09B0220-0600