D12320VF25IV Datasheet, PDF (570/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 11 Programmable Pulse Generator (PPG)
Address H'FF4D
Bit
:
Initial value :
R/W
:
7
NDR7
0
R/W
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
Address H'FF4F
Bit
:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value :
1
1
1
1
1
1
1
1
R/W
:—
—
—
—
—
—
—
—
Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by
different compare match events, the address of the upper 4 bits in NDRH (group 3) is H'FF4C and
the address of the lower 4 bits (group 2) is H'FF4E. Bits 3 to 0 of address H'FF4C and bits 7 to 4
of address H'FF4E are reserved bits that cannot be modified and are always read as 1.
Address H'FF4C
Bit
:
7
6
5
4
3
2
1
0
NDR15 NDR14 NDR13 NDR12 —
—
—
—
Initial value :
0
0
0
0
1
1
1
1
R/W
: R/W
R/W
R/W
R/W
—
—
—
—
Address H'FF4E
Bit
:
7
6
5
4
3
2
1
0
—
—
—
— NDR11 NDR10 NDR9 NDR8
Initial value :
1
1
1
1
0
0
0
0
R/W
:—
—
—
—
R/W
R/W
R/W
R/W
If pulse output groups 0 and 1 are triggered by different compare match event, the address of the
upper 4 bits in NDRL (group 1) is H'FF4D and the address of the lower 4 bits (group 0) is H'FF4F.
Bits 3 to 0 of address H'FF4D and bits 7 to 4 of address H'FF4F are reserved bits that cannot be
modified and are always read as 1.
Rev.6.00 Sep. 27, 2007 Page 538 of 1268
REJ09B0220-0600