D12320VF25IV Datasheet, PDF (1107/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
Module Register
Abbreviation R/W Initial Value Address^*1
Port C
Port C data direction register
PCDDR
W
H'00
H'FEBB
Port C data register
PCDR
R/W H'00
H'FF6B
Port C register
PORTC
R
Undefined H'FF5B
Port C MOS pull-up control register PCPCR
R/W H'00
H'FF72
Port D
Port D data direction register
PDDDR
W
H'00
H'FEBC
Port D data register
PDDR
R/W H'00
H'FF6C
Port D register
PORTD
R
Undefined H'FF5C
Port D MOS pull-up control register PDPCR
R/W H'00
H'FF73
Port E
Port E data direction register
PEDDR
W
H'00
H'FEBD
Port E data register
PEDR
R/W H'00
H'FF6D
Port E register
PORTE
R
Undefined H'FF5D
Port F
Port E MOS pull-up control register PEPCR
Port F data direction register
PFDDR
R/W H'00
H'FF74
W
H'80/H'00^*20 H'FEBE
Port F data register
PFDR
R/W H'00
H'FF6E
Port F register
PORTF
R
Undefined H'FF5E
Port function control register 2
PFCR2
R/W H'30
H'FFAC
System control register
SYSCR
R/W H'01
H'FF39
Port G Port G data direction register
PGDDR
W
H'10/H'00
*²⁰ *²¹
H'FEBF
Port G data register
Port G register
PGDR
PORTG
R/W
R
H'00^*21
H'FF6F
Undefined^*21 H'FF5F
Port function control register 2
PFCR2
R/W H'30
H'FFAC
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
Lower 16 bits of the address.
Only 0 can be written for flag clearing.
Registers in the DTC cannot be read or written to directly.
Located as register information in on-chip RAM addresses H'EBC0 to H'EFBF. Cannot
be located in external memory space. Do not clear the RAME bit in SYSCR to 0 when
using the DTC.
Determined by the MCU operating mode.
Reserved in the H8S/2321.
The DMAC is not supported in the H8S/2321.
Bits used for pulse output cannot be written to.
Rev.6.00 Sep. 27, 2007 Page 1075 of 1266
REJ09B0220-0600