D12320VF25IV Datasheet, PDF (950/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 20 Clock Pulse Generator
20.4 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (φ).
20.5 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
20.6 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed
clocks (φ/2, φ/4, φ/8, φ/16, or φ/32) to be supplied to the bus master, according to the settings of
the SCK2 to SCK0 bits in SCKCR.
Rev.6.00 Sep. 27, 2007 Page 918 of 1268
REJ09B0220-0600