D12320VF25IV Datasheet, PDF (900/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 ROM
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit
enables the flash memory control registers to be read and written to. Clearing FLSHE to 0
designates these registers as unselected (the register contents are retained).
Bit 3
FLSHE
0
1
Description
Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB
(Initial value)
Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB
Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0.
19.23.6 RAM Emulation Register (RAMER)
Bit
:
7
6
5
4
—
—
—
—
Initial value :
0
0
0
0
R/W
:—
—
—
—
3
RAMS
0
R/W
2
RAM2
0
R/W
1
RAM1
0
R/W
0
RAM0
0
R/W
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware
standby mode. It is not initialized in software standby mode. RAMER settings should be made in
user mode or user program mode.
Flash memory area divisions are shown in table 19.50. To ensure correct operation of the
emulation function, the ROM for which RAM emulation is performed should not be accessed
immediately after this register has been modified. Normal execution of an access immediately
after register modification is not guaranteed.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.
Rev.6.00 Sep. 27, 2007 Page 868 of 1268
REJ09B0220-0600