D12320VF25IV Datasheet, PDF (1110/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
MRB—DTC Mode Register B
H'F800—H'FBFF
DTC
Bit
:
Initial value :
Read/Write :
7
6
5
4
3
2
1
0
CHNE DISEL CHNS —
—
—
—
—
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
—
—
—
—
—
—
—
—
Reserved
Only 0 should be written to these bits
DTC Chain Transfer Select
DTC Interrupt Select
0 After DTC data transfer ends, the CPU interrupt is
disabled unless the transfer counter is 0
1 After DTC data transfer ends, the CPU interrupt is enabled
DTC Chain Transfer Enable
CHNE CHNS
Description
0 — No chain transfer. (At end of DTC data
transfer, DTC waits for activation)
1
0 Chain transfer every time
1
1 Chain transfer only when transfer counter = 0
SAR—DTC Source Address Register
H'F800—H'FBFF
DTC
Bit
: 23 22 21 20 19
---
43210
---
Initial value : Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
---
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
Read/Write : — — — — —
---
— — —— —
Specifies DTC transfer data source address
DAR—DTC Destination Address Register
H'F800—H'FBFF
DTC
Bit
: 23 22 21 20 19
---
43210
---
Initial value : ^{Unde- Unde- Unde- Unde- Unde-}
---
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
fined fined fined fined fined
Read/Write : — — — — —
---
—————
Specifies DTC transfer data destination address
Rev.6.00 Sep. 27, 2007 Page 1078 of 1268
REJ09B0220-0600