D12320VF25IV Datasheet, PDF (573/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 11 Programmable Pulse Generator (PPG)
11.2.6 PPG Output Mode Register (PMR)
Bit
:
Initial value :
R/W
:
7
G3INV
1
R/W
6
G2INV
1
R/W
5
G1INV
1
R/W
4
G0INV
1
R/W
3
G3NOV
0
R/W
2
G2NOV
0
R/W
1
G1NOV
0
R/W
0
G0NOV
0
R/W
PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping
operation for each group.
The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB
and the non-overlap margin is set in TGRA. The output values change at compare match A and B.
For details, see section 11.3.4, Non-Overlapping Pulse Output.
PMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Group 3 Inversion (G3INV): Selects direct output or inverted output for pulse output
group 3 (pins PO15 to PO12).
Bit 7
G3INV
0
1
Description
Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH)
Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH)
(Initial value)
Bit 6—Group 2 Inversion (G2INV): Selects direct output or inverted output for pulse output
group 2 (pins PO11 to PO8).
Bit 6
G2INV
0
1
Description
Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH)
Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH)
(Initial value)
Rev.6.00 Sep. 27, 2007 Page 541 of 1268
REJ09B0220-0600