D12320VF25IV Datasheet, PDF (607/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 8-Bit Timers
12.6.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T₂ state of a TCNT write cycle, the write
takes priority and the counter is not incremented.
Figure 12.11 shows this operation.
TCNT write cycle by CPU
T₁
T₂
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 12.11 Contention between TCNT Write and Increment
Rev.6.00 Sep. 27, 2007 Page 575 of 1268
REJ09B0220-0600