D12320VF25IV Datasheet, PDF (710/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 Smart Card Interface
15.3 Operation
15.3.1 Overview
The main functions of the smart card interface are as follows.
• One frame consists of 8-bit data plus a parity bit.
• In transmission, a guard time of at least 2 etu (1 etu in block transfer mode) (elementary time
unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the
next frame.
• If a parity error is detected during reception, a low error signal level is output for one etu
period, 10.5 etu after the start bit. (This does not apply to block transfer mode.)
• If the error signal is sampled during transmission, the same data is transmitted automatically
after the elapse of 2 etu or longer. (This does not apply to block transfer mode.)
• Only asynchronous communication is supported; there is no synchronous communication
function.
15.3.2 Pin Connections
Figure 15.2 shows a schematic diagram of smart card interface related pin connections.
In communication with an IC card, since both transmission and reception are carried out on a
single data communication line, the chip’s TxD pin and RxD pin should both be connected to the
line, as shown in the figure. The data communication line should be pulled up to the V_CC power
supply with a resistor.
When the clock generated on the smart card interface is used by an IC card, the SCK pin output is
input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock.
Chip port output is used as the reset signal.
Other pins must normally be connected to the power supply or ground.
Rev.6.00 Sep. 27, 2007 Page 678 of 1268
REJ09B0220-0600