D12320VF25IV Datasheet, PDF (738/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 16 A/D Converter (8 Analog Input Channel Version)
16.2.2 A/D Control/Status Register (ADCSR)
Bit
:
Initial value :
R/W
:
7
ADF
0
R/(W)^*
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
0
CH0
0
R/W
Note: * Only 0 can be written to bit 7, to clear this flag.
ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows
the status of the operation.
ADCSR is initialized to H'00 by a reset, and in standby mode or module stop mode.
Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
Bit 7
ADF
Description
0
[Clearing conditions]
(Initial value)
• When 0 is written to the ADF flag after reading ADF = 1
• When the DMAC^* or DTC is activated by an ADI interrupt and ADDR is read
1
[Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When A/D conversion ends on all specified channels
Note: * The DMAC is not supported in the H8S/2321.
Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests
at the end of A/D conversion.
Bit 6
ADIE
0
1
Description
A/D conversion end interrupt (ADI) request disabled
A/D conversion end interrupt (ADI) request enabled
(Initial value)
Rev.6.00 Sep. 27, 2007 Page 706 of 1268
REJ09B0220-0600