D12320VF25IV Datasheet, PDF (274/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
Bit 6—Destination Address Increment/Decrement (DAID)
Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify
whether destination address register MARB is to be incremented, decremented, or left unchanged,
when data transfer is performed.
Bit 6
DAID
0
1
Bit 5
DAIDE
0
1
0
1
Description
MARB is fixed
(Initial value)
MARB is incremented after a data transfer
• When DTSZ = 0, MARB is incremented by 1 after a transfer
• When DTSZ = 1, MARB is incremented by 2 after a transfer
MARB is fixed
MARB is decremented after a data transfer
• When DTSZ = 0, MARB is decremented by 1 after a transfer
• When DTSZ = 1, MARB is decremented by 2 after a transfer
Bit 4—Reserved: Can be read or written to. Only 0 should be written to this bit.
Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor
(activation source). The factors that can be specified differ between normal mode and block
transfer mode.
• Normal Mode
Bit 3
DTF3
0
1
Bit 2
DTF2
0
1
*
Bit 1
DTF1
0
1
0
1
*
Bit 0
DTF0
0
1
0
1
*
0
1
*
Description
—
—
Activated by DREQ pin falling edge input
Activated by DREQ pin low-level input
—
Auto-request (cycle steal)
Auto-request (burst)
—
(Initial value)
*: Don't care
Rev.6.00 Sep. 27, 2007 Page 242 of 1268
REJ09B0220-0600