D12320VF25IV Datasheet, PDF (798/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 ROM
elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in
FLMCR1. The time during which the P bit is set is the flash memory programming time. Set the
programming time according to the table in the programming flowchart.
19.7.2 Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the P bit in
FLMCR1 is cleared to 0, then the PSU bit is cleared to 0 at least (α) µs later). Next, the watchdog
timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to program-
verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy
write of H'FF data should be made to the addresses to be read. The dummy write should be
executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data
is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy
write before performing this read operation. Next, the originally written data is compared with the
verify data, and reprogram data is computed (see figure 19.14) and transferred to the reprogram
data area. After 128 bytes of data have been verified, exit program-verify mode in FLMCR1 to 0,
and wait again for at least (θ) μs. If reprogramming is necessary, set program mode again, and
repeat the program/program-verify sequence as before. However, ensure that the
program/program-verify sequence is not repeated more than (N) times on the same bits.
Rev.6.00 Sep. 27, 2007 Page 766 of 1268
REJ09B0220-0600