D12320VF25IV Datasheet, PDF (769/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 ROM
19.2.2 Bus Control Register L (BCRL)
Bit
:
7
6
5
4
3
2
1
0
BRLE BREQOE EAE
—
DDS
—
WDBE WAITE
Initial value :
0
0
1
1
1
1
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enabling or disabling of part of the on-chip ROM area in the chip can be selected by means of the
EAE bit in BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L
(BCRL).
Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'03FFFF*² are
to be internal addresses or external addresses.
Description
Bit 5
0
1
H8S/2329B, H8S/2328^*3,
H8S/2326
H8S/2327
H8S/2323
On-chip ROM
Addresses H'010000 to
H'01FFFF are on-chip
ROM or address H'020000
to H'03FFFF are reserved
area^*1
Reserved area^*1
Addresses H'010000 to H'03FFFF^*2 are external addresses in external expanded mode
or reserved area^*1 in single-chip mode
(Initial value)
Notes: 1. Do not access a reserved area.
2. Addresses H'010000 to H'05FFFF in the H8S/2329B.
Addresses H'010000 to H'07FFFF in the H8S/2326.
3. H8S/2328B in flash memory version.
19.3 Operation
The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can
be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to
the lower 8 bits. Word data must start at an even address.
The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0) and the EAE
bit in BCRL. These settings are shown in tables 19.2 and 19.3.
Rev.6.00 Sep. 27, 2007 Page 737 of 1268
REJ09B0220-0600