D12320VF25IV Datasheet, PDF (557/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T₂ state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the
data prior to the write.
Figure 10.52 shows the timing in this case.
TGR write cycle
T₁
T₂
φ
Address
Buffer register
address
Write signal
Compare
match signal
Buffer
register
Buffer register write data
N
M
TGR
N
Figure 10.52 Contention between Buffer Register Write and Compare Match
Rev.6.00 Sep. 27, 2007 Page 525 of 1268
REJ09B0220-0600