D12320VF25IV Datasheet, PDF (1188/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
SMR0—Serial Mode Register 0
H'FF78
Smart Card Interface 0
Bit
:
7
6
5
4
3
2
1
0
GM
BLK
PE
O/E BCP1 BCP0 CKS1 CKS0
Initial value :
0
0
0
0
0
0
0
0
Read/Write : R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select
0 0 φ clock
1 φ/4 clock
1 0 φ/16 clock
1 φ/64 clock
Base Clock Pulse
BCP1 BCP0 Base Clock Pulse
0 0 32 clocks
1 64 clocks
1 0 372 clocks
1 256 clocks
Parity Mode
0 Even parity
1 Odd parity
Parity Enable
(Set to 1 when using the smart card interface)
0 Setting prohibited
1 Parity bit addition and checking enabled
Block Transfer Mode Select
0 Normal smart card interface mode
GSM Mode
1 Block transfer mode
0 Normal smart card interface mode operation
• TEND flag generated 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit
• Clock output on/off control only
1 GSM mode smart card interface mode operation
• TEND flag generated 11.0 etu after beginning of start bit
• Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control
Note: etu: Elementary time unit (time for transfer of 1 bit)
Rev.6.00 Sep. 27, 2007 Page 1156 of 1268
REJ09B0220-0600