D12320VF25IV Datasheet, PDF (247/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.11.4 External Bus Release Usage Note
External bus release can be performed on completion of an external bus cycle. The RD signal and
the DRAM interface* RAS and CAS signals remain low until the end of the external bus cycle.
Therefore, when external bus release is performed, the RD, RAS, and CAS signals may change
from the low level to the high-impedance state.
Note: * The DRAM interface is not supported in the H8S/2321.
6.12 Resets and the Bus Controller
In a reset, the chip, including the bus controller, enters the reset state at that point, and any
executing bus cycle is discontinued.
Rev.6.00 Sep. 27, 2007 Page 215 of 1268
REJ09B0220-0600