D12320VF25IV Datasheet, PDF (321/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
DREQ Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the
DREQ pin is selected to 1.
Figure 7.25 shows an example of DREQ level activated normal mode transfer.
Bus
release
DMA
read
DMA
write
Bus
release
DMA
read
DMA
write
Bus
release
φ
DREQ
Address
bus
DMA
control
Idle
Transfer source Transfer destination
Read Write
Idle
Transfer source Transfer destination
Read Write
Idle
Channel
Request
Request clear period
Minimum
of 2 cycles
Request
Minimum
of 2 cycles
Request clear period
[1] [2] [3]
[4] [5] [6]
[7]
Acceptance resumes
Acceptance resumes
[1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the write cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.25 Example of DREQ Level Activated Normal Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
Rev.6.00 Sep. 27, 2007 Page 289 of 1268
REJ09B0220-0600