D12320VF25IV Datasheet, PDF (943/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 20 Clock Pulse Generator
Section 20 Clock Pulse Generator
20.1 Overview
The chip has an on-chip clock pulse generator (CPG) that generates the system clock (φ), the bus
master clock, and internal clocks.
The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium-
speed clock divider, and a bus master clock selection circuit.
In the chip, the CPG has a medium-speed mode in which the bus master runs on a medium-speed
clock and the other supporting modules run on the high-speed clock, and a function that allows the
medium-speed mode to be disabled and the clock division ratio to be changed for the entire chip.
A clock from φ/2 to φ/32 can be selected.
20.1.1 Block Diagram
Figure 20.1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Oscillator
Duty
adjustment
circuit
SCKCR
SCK2 to SCK0
Medium-
speed clock
divider
DIV
φ/2 to φ/32
Bus master
clock
selection
circuit
System clock Internal clock
to φ pin
to supporting
modules
Bus master clock
to CPU, DTC,
and DMAC*
Note: * The DMAC is not supported in the H8S/2321.
Figure 20.1 Block Diagram of Clock Pulse Generator
Rev.6.00 Sep. 27, 2007 Page 911 of 1268
REJ09B0220-0600