D12320VF25IV Datasheet, PDF (1141/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
MCR—Memory Control Register
(Not supported in H8S/2321)
H'FED6
Bus Controller
Bit
:
Initial value :
Read/Write :
7
TPC
0
R/W
6
5
4
3
2
1
0
BE RCDM — MXC1 MXC0 RLW1 RLW0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
Refresh Cycle Wait Control
0 0 No wait state inserted
1 1 wait state inserted
1 0 2 wait states inserted
1 3 wait states inserted
Multiplex Shift Count
0 0 8-bit shift
1 9-bit shift
1 0 10-bit shift
1—
Reserved
RAS Down Mode
0 RAS up mode selected for DRAM interface
1 RAS down mode selected for DRAM interface
Burst Access Enable
0 Burst disabled (always full access)
1 _{For DRAM space access, access in fast page mode}
TP Cycle Control
0 1-state precharge cycle is inserted
1 2-state precharge cycle is inserted
Rev.6.00 Sep. 27, 2007 Page 1109 of 1268
REJ09B0220-0600