D12320VF25IV Datasheet, PDF (427/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9.8.2 Register Configuration
Table 9.13 shows the port A register configuration.
Table 9.13 Port A Registers
Name
Abbreviation R/W
Port A data direction register
PADDR
W
Port A data register
PADR
R/W
Port A register
PORTA
R
Port A MOS pull-up control register PAPCR
R/W
Port A open drain control register PAODR
R/W
Port function control register 1
PFCR1
R/W
System control register
SYSCR
R/W
Note: * Lower 16 bits of the address.
Section 9 I/O Ports
Initial Value
H'00
H'00
Undefined
H'00
H'00
H'0F
H'01
Address^*
H'FEB9
H'FF69
H'FF59
H'FF70
H'FF77
H'FF45
H'FF39
Port A Data Direction Register (PADDR)
Bit
:
7
6
5
4
3
2
1
0
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
:W
W
W
W
W
W
W
W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
PADDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.
Rev.6.00 Sep. 27, 2007 Page 395 of 1268
REJ09B0220-0600