D12320VF25IV Datasheet, PDF (1221/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
TCSR0—Timer Control/Status Register 0
TCSR1—Timer Control/Status Register 1
H'FFB2
H'FFB3
8-Bit Timer Channel 0
8-Bit Timer Channel 1
TCSR0 Bit
:7
6
5
4
3
2
1
0
CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0
Initial value : 0
0
0
0
0
0
0
0
Read/Write : R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W
TCSR1 Bit
:7
6
5
4
CMFB CMFA OVF
—
Initial value : 0
0
0
1
Read/Write : ^{R/(W)* R/(W)* R/(W)* —}
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
Output Select
0 0 No change when compare
match A occurs
1 0 is output when compare
match A occurs
1 0 1 is output when compare
match A occurs
1 Output is inverted when
compare match A
occurs (toggle output)
Output Select
0 0 No change when compare match B occurs
1 0 is output when compare match B occurs
1 0 1 is output when compare match B occurs
1 Output is inverted when compare match B
occurs (toggle output)
A/D Trigger Enable (TCSR0 only)
0 A/D converter start requests by compare match A are disabled
1 A/D converter start requests by compare match A are enabled
Timer Overflow Flag
0 [Clearing condition]
When 0 is written to OVF after reading OVF = 1
1 [Setting condition]
When TCNT overflows (changes from H'FF to H'00)
Compare Match Flag A
0 [Clearing conditions]
• When 0 is written to CMFA after reading CMFA = 1
• When the DTC is activated by a CMIA interrupt, while the DISEL bit of MRB in DTC is 0
1 [Setting condition]
When TCNT matches TCORA
Compare Match Flag B
0 [Clearing conditions]
• When 0 is written to CMFB after reading CMFB = 1
• When the DTC is activated by a CMIB interrupt, while the DISEL bit of MRB in DTC is 0
1 [Setting condition]
When TCNT matches TCORB
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Rev.6.00 Sep. 27, 2007 Page 1189 of 1268
REJ09B0220-0600