D12320VF25IV Datasheet, PDF (189/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6.2.5 Bus Control Register L (BCRL)
Bit
:
Initial value :
R/W
:
7
BRLE
0
R/W
6
BREQOE
0
R/W
5
EAE
1
R/W
Note: * This bit is reserved in the H8S/2321.
Section 6 Bus Controller
4
3
2
1
0
—
DDS^*
— WDBE^* WAITE
1
1
1
0
0
R/W
R/W
R/W
R/W
R/W
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, DMAC single address transfer, enabling or disabling of the write data buffer
function, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
0
1
Description
External bus release is disabled. BREQ, BACK, and BREQO pins can be used as I/O
ports
(Initial value)
External bus release is enabled
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus release state, when an internal bus
master performs an external space access, or when a refresh request is generated.
Bit 6
BREQOE
0
1
Description
BREQO output disabled. BREQO pin can be used as I/O port
BREQO output enabled
(Initial value)
Rev.6.00 Sep. 27, 2007 Page 157 of 1268
REJ09B0220-0600