D12320VF25IV Datasheet, PDF (113/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 MCU Operating Modes
3.2.2 System Control Register (SYSCR)
Bit
:
7
—
Initial value :
0
R/W
: R/W
6
5
4
3
2
1
0
—
INTM1 INTM0 NMIEG LWROD IRQPAS RAME
0
0
0
0
0
0
1
—
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7—Reserved: Only 0 should be written to this bit.
Bit 6—Reserved: This bit is always read as 0, and cannot be modified.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control
mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,
Interrupt Control Modes and Interrupt Operation.
Bit 5
INTM1
0
1
Bit 4
INTM0
0
1
0
1
Interrupt Control
Mode
Description
0
Control of interrupts by I bit
(Initial value)
—
Setting prohibited
2
Control of interrupts by I2 to I0 bits and IPR
—
Setting prohibited
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG
0
1
Description
An interrupt is requested at the falling edge of NMI input
An interrupt is requested at the rising edge of NMI input
(Initial value)
Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output.
Bit 2
LWROD
0
1
Description
PF3 is designated as LWR output pin
PF3 is designated as I/O port, and does not function as LWR output pin
(Initial value)
Rev.6.00 Sep. 27, 2007 Page 81 of 1268
REJ09B0220-0600