D12320VF25IV Datasheet, PDF (273/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
Bit 14—Source Address Increment/Decrement (SAID)
Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether
source address register MARA is to be incremented, decremented, or left unchanged, when data
transfer is performed.
Bit 14
SAID
0
1
Bit 13
SAIDE
0
1
0
1
Description
MARA is fixed
(Initial value)
MARA is incremented after a data transfer
• When DTSZ = 0, MARA is incremented by 1 after a transfer
• When DTSZ = 1, MARA is incremented by 2 after a transfer
MARA is fixed
MARA is decremented after a data transfer
• When DTSZ = 0, MARA is decremented by 1 after a transfer
• When DTSZ = 1, MARA is decremented by 2 after a transfer
Bit 12—Block Direction (BLKDIR)
Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode
is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side
or the destination side is to be the block area.
Bit 12
BLKDIR
0
1
Bit 11
BLKE
0
1
0
1
Description
Transfer in normal mode
(Initial value)
Transfer in block transfer mode, destination side is block area
Transfer in normal mode
Transfer in block transfer mode, source side is block area
For operation in normal mode and block transfer mode, see section 7.5, Operation.
Bits 10 to 7—Reserved: Can be read or written to. Only 0 should be written to these bits.
Rev.6.00 Sep. 27, 2007 Page 241 of 1268
REJ09B0220-0600