D12320VF25IV Datasheet, PDF (878/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 ROM
φ
VCC
FWE
MD2 to MD0^*1
RES
SWE bit
Programming/
erasing
Wait time: x possible
Wait time: 100 μs
tOSC1
Min 0 μs
tMDS^*3
tMDS^*3
SWE set
Min 0 μs
SWE cleared
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit)^*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
Notes: 1.
2.
3.
Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until
power-off by pulling the pins up or down.
See section 22.2.6, Flash Memory Characteristics.
Mode programming setup time tMDS (min) = 200 ns
Figure 19.56 Power-On/Off Timing (Boot Mode)
Rev.6.00 Sep. 27, 2007 Page 846 of 1268
REJ09B0220-0600