D12320VF25IV Datasheet, PDF (1297/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix D Pin States
Port Name
Pin Name
PG0/CAS^*3
MCU
Operating
Mode
4 to 6
Reset
T
Hardware
Standby
Mode
T
Software
Standby Mode
[DRAME^*4 = 0]
kept
[DRAME^*4 ·
OPE = 1]
T
[DRAME^*4 ·
OPE = 1]
CAS^*3
Bus-Released
State
T
Program
Execution State
Sleep Mode
[DRAME^*4 = 0]
Input port
[DRAME^*4 = 1]
CAS^*3
7
T
T
kept
kept
I/O port
Legend:
H:
High level
L:
Low level
T:
High impedance
kept:
Input port becomes high-impedance, output port retains state
DDR:
Data direction register
OPE:
Output port enable
WAITE: Wait input enable
WAITPS: WAIT pin select
BRLE:
Bus release enable
BREQOE: BREQO pin enable
BREQOPS: BREQO pin select
DRAME: DRAM space setting
LCASE: DRAM space setting, 16-bit access setting
AnE:
Address n enable (n = 23 to 21)
A20E:
Address 20 enable
ASOD: AS output disable
CS167E: CS167 enable
CS25E: CS25 enable
LWROD: LWR output disable
Notes: 1. LCAS is not supported in the H8S/2321.
2. As the DRAM interface is not supported in the H8S/2321, LCASE is always 0.
3. CAS is not supported in the H8S/2321.
4. As the DRAM interface is not supported in the H8S/2321, DRAME is always 0.
5. The WDTOVF pin function is not usable on the F-ZTAT version.
6. A low level is output if a WDT overflow occurs while WT/IT is set to 1.
Rev.6.00 Sep. 27, 2007 Page 1265 of 1268
REJ09B0220-0600