D12320VF25IV Datasheet, PDF (379/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 I/O Ports
Section 9 I/O Ports
9.1 Overview
The chip has 12 I/O ports (ports 1, 2, 3, 5, 6, and A to G), and one input-only port (port 4).
Table 9.1 summarizes the port functions. The pins of each port also have other functions.
Each port includes a data direction register (DDR) that controls input/output (not provided for the
input-only port), a data register (DR) that stores output data, and a port register (PORT) used to
read the pin states.
Ports A to E have a built-in MOS pull-up function, and in addition to DR and DDR, have a MOS
input pull-up control register (PCR) to control the on/off state of MOS input pull-up.
Port 3 and port A include an open drain control register (ODR) that controls the on/off state of the
output buffer PMOS.
Ports 1 and A to F can drive a single TTL load and 50 pF capacitive load, and ports 2, 3, 5, 6, and
G can drive a single TTL load and 30 pF capacitive load.
Ports 1, 2, and 5 (only when used for IRQ input), and pins 6₄ to 6₇ and A₄ to A₇, are Schmitt-
triggered inputs.
Rev.6.00 Sep. 27, 2007 Page 347 of 1268
REJ09B0220-0600