D12320VF25IV Datasheet, PDF (217/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.5.5 Pins Used for DRAM Interface
Table 6.7 shows the pins used for DRAM interfacing and their functions.
Table 6.7 DRAM Interface Pins
Pin
HWR
With DRAM
Setting
WE
Name
Write enable
LCAS
LCAS
CS2
RAS2
CS3
RAS3
CS4
RAS4
CS5
RAS5
CAS
UCAS
WAIT
A12 to A0
WAIT
A12 to A0
D15 to D0 D15 to D0
Lower column address
strobe
Row address strobe 2
Row address strobe 3
Row address strobe 4
Row address strobe 5
Upper column address
strobe
Wait
Address pins
Data pins
I/O
Output
Output
Output
Output
Output
Output
Output
Input
Output
I/O
Function
When 2-CAS system is set,
write enable for DRAM space
access
Lower column address strobe
for 16-bit DRAM space access
Row address strobe when area
2 is designated as DRAM space
Row address strobe when area
3 is designated as DRAM space
Row address strobe when area
4 is designated as DRAM space
Row address strobe when area
5 is designated as DRAM space
Upper column address strobe
for DRAM space access
Wait request signal
Row address/column address
multiplexed output
Data input/output pins
Rev.6.00 Sep. 27, 2007 Page 185 of 1268
REJ09B0220-0600