D12320VF25IV Datasheet, PDF (291/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission data empty/reception data full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can be set for channel B only.
Figure 7.4 shows an example of the setting procedure for sequential mode.
Sequential mode setting
Set DMABCRH
[1]
Set transfer source
and transfer destination _[2]
addresses
Set number of transfers ^[3]
Set DMACR
[4]
Read DMABCRL
[5]
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in ETCR.
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Clear the RPE bit to 0 to select sequential
mode.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set the DTE bit to 1 to enable transfer.
Set DMABCRL
[6]
Sequential mode
Figure 7.4 Example of Sequential Mode Setting Procedure
Rev.6.00 Sep. 27, 2007 Page 259 of 1268
REJ09B0220-0600