D12320VF25IV Datasheet, PDF (238/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
Usage Notes: When DRAM space* is accessed, the ICIS0 and ICIS1 bit settings are disabled. In
the case of consecutive reads between different areas, for example, if the second access is a
DRAM access*, only a T_p cycle is inserted, and a T_I cycle is not. The timing in this case is shown
in figure 6.34.
However, in burst access in RAS down mode these settings are enabled, and an idle cycle is
inserted. The timing in this case is shown in figures 6.35 (a) and (b).
Note: * The DRAM interface is not supported in the H8S/2321.
φ
Address bus
RD
Data bus
External read
T₁ T₂ T₃
DRAM space read
T_p
T_r
T_c1 T_c2
Figure 6.34 Example of DRAM Access after External Read
Rev.6.00 Sep. 27, 2007 Page 206 of 1268
REJ09B0220-0600