D12320VF25IV Datasheet, PDF (765/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 18 RAM
18.3 Operation
When the RAME bit is set to 1, accesses to addresses H'FFDC00 to H'FFFBFF are directed to the
on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to
and read in byte or word units. Each type of access can be performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
Note: The amount of on-chip RAM differs depending on the product. Refer to section 3.5,
Memory Map in Each Operation Mode, for details.
18.4 Usage Note
DTC register information can be located in addresses H'FFF800 to H'FFFBFF. When the DTC is
used, the RAME bit must not be cleared to 0.
Rev.6.00 Sep. 27, 2007 Page 733 of 1268
REJ09B0220-0600