 English |
|
|
|
|
|
|
|
| D12320VF25IV Datasheet, PDF (81/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
| |||
| ◁ |
Section 2 CPU
2.6.2 Instructions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU
can use.
Table 2.2 Combinations of Instructions and Addressing Modes
Addressing Modes
Function Instruction
Data
transfer
MOV
BWL BWL BWL BWL BWL BWL B BWL â BWL â â â â
POP, PUSH â â â â â â â â â â â â â WL
LDM, STM
â
â
â
ââ
â
ââ
â
ââ
â
â
L
MOVFPE,
âââââââ B ââââââ
MOVTPE*1
Arithmetic ADD, CMP BWL BWL â â â â â â â â â â â â
operations SUB
WL BWL â â â â â â â â â â â â
ADDX, SUBX B
B
ââââââââââââ
ADDS, SUBS â
L
ââââââââââââ
INC, DEC
â BWL â â â â â â â â â â â â
DAA, DAS
â B â â â â â â â â â â ââ
MULXU,
DIVXU
â BW â â â â â â â â â â â â
MULXS,
DIVXS
â BW â â â â â â â â â â â â
NEG
â BWL â â â â â â â â â â â â
EXTU, EXTS â WL â â â â â â â â â â â â
TAS*2
ââ B âââââââââââ
Logic
AND, OR,
operations XOR
BWL BWL â â â â â â â â â â â â
NOT
â BWL â â â â â â â â â â â â
Shift
â BWL â â â â â â â â â â â â
Bit manipulation
âB
B
âââ B
B â B ââââ
Branch
Bcc, BSR
ââââââââââ
ââ
JMP, JSR
ââââââââ
âââ
â
RTS
âââââââââââââ
System
control
TRAPA
RTE
âââââââââââââ
âââââââââââââ
SLEEP
âââââââââââââ
LDC
B
B
WWWWâWâWââââ
STC
â B WWWWâWâWââââ
ANDC,
B âââââââââââââ
ORC, XORC
NOP
âââââââââââââ
Block data transfer
â â â â â â â â â â â â â BW
Legend:
B: Byte
W: Word
L: Longword
Notes: 1. Cannot be used in the H8S/2329 Group and H8S/2328 Group.
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev.6.00 Sep. 27, 2007 Page 49 of 1268
REJ09B0220-0600
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese