D12320VF25IV Datasheet, PDF (220/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.5.8 Wait Control
There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and
pin wait insertion using the WAIT pin.
Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM
space is set to 1, from 0 to 3 wait states can be inserted automatically between the T_c1 state and T_c2
state, according to the settings of WCRH and WCRL.
Pin Wait Insertion: When the WAITE bit in BCRH is set to 1, wait input by means of the WAIT
pin is enabled regardless of the setting of the AST bit in ASTCR. When DRAM space is accessed
in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of φ in the
last T_c1 or T_w state, another T_w state is inserted. If the WAIT pin is held low, T_w states are inserted
until it goes high.
Figure 6.17 shows an example of wait state insertion timing.
Rev.6.00 Sep. 27, 2007 Page 188 of 1268
REJ09B0220-0600