D12320VF25IV Datasheet, PDF (289/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
• External request
In response to a single transfer request, the specified number of transfers are carried out, one
byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the
specified number of transfers have been completed. Both addresses are specified as 24 bits.
Block Transfer Mode: In response to a single transfer request, a block transfer of the specified
block size is carried out. This is repeated the specified number of times, once each time there is a
transfer request. At the end of each single block transfer, one address is restored to its original
setting. An interrupt request can be sent to the CPU or DTC when the specified number of block
transfers have been completed. Both addresses are specified as 24 bits.
7.5.2 Sequential Mode
Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,
MAR is updated after each byte or word transfer in response to a single transfer request, and this is
executed the number of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 7.6 summarizes register functions in sequential mode.
Table 7.6 Register Functions in Sequential Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
Operation
23
MAR
0 Source
address
register
Destination Start address of Incremented/
address transfer destination decremented every
register or transfer source transfer
23
15
H'FF
IOAR
0 Destination Source
address address
register register
Start address of Fixed
transfer source or
transfer destination
15
0 Transfer counter
ETCR
Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
DTDIR: Data transfer direction bit
Rev.6.00 Sep. 27, 2007 Page 257 of 1268
REJ09B0220-0600