D12320VF25IV Datasheet, PDF (340/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
φ
Internal address
DMA
read
DMA
write
Internal read signal
Internal write signal
External address
HWR, LWR
TEND
Not output
External write by CPU, etc.
Figure 7.42 Example in Which Low Level is Not Output at TEND Pin
Activation by Falling Edge on DREQ Pin: DREQ pin falling edge detection is performed in
synchronization with DMAC internal operations. The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and
switches to [2].
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and
switches to [1].
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is
enabled is performed on detection of a low level.
Activation Source Acceptance: At the start of activation source acceptance, a low level is
detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an
internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an
internal interrupt or DREQ pin low level that occurs before execution of the DMABCRL write to
enable transfer.
When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ
pin low level remaining from the end of the previous transfer, etc.
Rev.6.00 Sep. 27, 2007 Page 308 of 1268
REJ09B0220-0600