D12320VF25IV Datasheet, PDF (338/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
(b) If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
register is read as shown in figure 7.41.
φ
DMA internal
address
DMA control
DMA register
operation
CPU longword read
MAR upper
word read
MAR lower
word read
DMA transfer cycle
DMA read
DMA write
Transfe
source
Transfer
destination
Idle
Read
Write
Idle
[1]
[2]
Note: The lower word of MAR is the updated value after the operation in [1].
Figure 7.41 Contention between DMAC Register Update and CPU Read
Module Stop: When the MSTP15 bit in MSTPCR is set to 1, the DMAC clock stops, and the
module stop state is entered. However, 1 cannot be written to the MSTP15 bit if any of the DMAC
channels is enabled. This setting should therefore be made when DMAC operation is stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
• Transfer end/break interrupt (DTE = 0 and DTIE = 1)
• TEND pin enable (TEE = 1)
• DACK pin enable (FAE = 0 and SAE = 1)
Medium-Speed Mode: When the DTA bit is 0, internal interrupt signals specified as DMAC
transfer sources are edge-detected.
In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting
modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt
source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is
generated, is less than one state with respect to the DMAC clock (bus master clock), edge
detection may not be possible and the interrupt may be ignored.
Also, in medium-speed mode, DREQ pin sampling is performed on the rising edge of the medium-
speed clock.
Rev.6.00 Sep. 27, 2007 Page 306 of 1268
REJ09B0220-0600