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D12320VF25IV Datasheet, PDF (176/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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Section 6 Bus Controller
⢠Idle cycle insertion
⯠An idle cycle can be inserted in case of an external read cycle between different areas
⯠An idle cycle can be inserted when an external read cycle is immediately followed by an
external write cycle
⢠Write buffer functions
⯠External write cycle and internal access can be executed in parallel
⯠DMAC* single address mode and internal access can be executed in parallel
⢠Bus arbitration function
⯠Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC
⢠Other features
⯠Refresh counter (refresh timer)* can be used as an interval timer
⯠External bus release function
Note: * The DRAM interface, DMAC, and refresh counter are not supported in the H8S/2321.
Rev.6.00 Sep. 27, 2007 Page 144 of 1268
REJ09B0220-0600
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