D12320VF25IV Datasheet, PDF (693/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 14 Serial Communication Interface (SCI)
Restrictions on Use of DMAC^* or DTC
• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 φ clock cycles after TDR is updated by the DMAC* or DTC.
Misoperation may occur if the transmit clock is input within 4 φ clocks after TDR is updated.
(Figure 14.22)
• When RDR is read by the DMAC* or DTC, be sure to set the activation source to the relevant
SCI receive-data-full interrupt (RXI).
Note: * The DMAC is not supported in the H8S/2321.
SCK
TDRE
Serial data
t
LSB
D0
D1
D2
D3
D4
D5
D6
D7
Note: When operating on an external clock, set t > 4 clocks.
Figure 14.22 Example of Synchronous Transmission Using DTC
Rev.6.00 Sep. 27, 2007 Page 661 of 1268
REJ09B0220-0600