D12320VF25IV Datasheet, PDF (1243/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
TSR1—Timer Status Register 1
H'FFE5
TPU1
Bit
:
Initial value :
Read/Write :
7
TCFD
1
R
6
5
4
3
—
TCFU TCFV
—
1
0
0
0
— R/(W)* R/(W)* —
2
1
0
—
TGFB TGFA
0
0
0
— R/(W)* R/(W)*
Input Capture/Output Compare Flag A
0 [Clearing conditions]
• When DTC is activated by TGIA interrupt while
DISEL bit of MRB in DTC is 0
• When DMAC^*1 is activated by TGIA interrupt
while DTA bit of DMABCR in DMAC^*1 is 1
• When 0 is written to TGFA after reading
TGFA = 1
1 [Setting conditions]
• When TCNT = TGRA while TGRA is functioning
as output compare register
• When TCNT value is transferred to TGRA by
input capture signal while TGRA is functioning
as input capture register
Note: 1. The DMAC is not supported in the H8S/2321.
Input Capture/Output Compare Flag B
0 [Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL
bit of MRB in DTC is 0
• When 0 is written to TGFB after reading TGFB = 1
1 [Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
output compare register
• When TCNT value is transferred to TGRB by input
capture signal while TGRB is functioning as input
capture register
Overflow Flag
0 [Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
1 [Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
Underflow Flag
0 _{[Clearing condition]}
When 0 is written to TCFU after reading TCFU = 1
1 [Setting condition]
When the TCNT value underflows (changes from H'0000 to H'FFFF)
Count Direction Flag
0 TCNT counts down
1 TCNT counts up
Note: * Can only be written with 0 for flag clearing.
Rev.6.00 Sep. 27, 2007 Page 1211 of 1268
REJ09B0220-0600