D12320VF25IV Datasheet, PDF (201/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.3.5 Chip Select Signals
The chip can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low
when the corresponding external space area is accessed.
Figure 6.3 shows an example of CSn (n = 0 to 7) output timing.
Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR)
for the port corresponding to the particular CSn pin and either the CS167 enable bit (CS167E) or
the CS25 enable bit (CS25E).
In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset.
Pins CS1 to CS7 are placed in the input state after a power-on reset, so the corresponding DDR
bits, and CS167E or CS25E, should be set to 1 when outputting signals CS1 to CS7.
In ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a power-
on reset, so the corresponding DDR bits, and CS167E or CS25E, should be set to 1 when
outputting signals CS0 to CS7.
For details, see section 9, I/O Ports.
When areas 2 to 5 are designated as DRAM space*, outputs CS2 to CS5 are used as RAS signals.
Note: * The DRAM interface is not supported in the H8S/2321.
φ
Address bus
Bus cycle
T₁
T₂
T₃
Area n external address
CSn
Figure 6.3 CSn Signal Output Timing (n = 0 to 7)
Rev.6.00 Sep. 27, 2007 Page 169 of 1268
REJ09B0220-0600