D12320VF25IV Datasheet, PDF (764/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 18 RAM
18.1.2 Register Configuration
The on-chip RAM is controlled by SYSCR. Table 18.1 shows the address and initial value of
SYSCR.
Table 18.1 RAM Register
Name
Abbreviation R/W
System control register
SYSCR
R/W
Note: * Lower 16 bits of the address.
Initial Value
H'01
Address^*
H'FF39
18.2 Register Descriptions
18.2.1 System Control Register (SYSCR)
Bit
:
7
—
Initial value :
0
R/W
: R/W
6
5
4
3
2
1
0
—
INTM1 INTM0 NMIEG LWROD IRQPAS RAME
0
0
0
0
0
0
1
—
R/W
R/W
R/W
R/W
R/W
R/W
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 5.2.1, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
Rev.6.00 Sep. 27, 2007 Page 732 of 1268
REJ09B0220-0600