D12320VF25IV Datasheet, PDF (898/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 ROM
19.23.4 Erase Block Registers 2 (EBR2)
Bit
:
7
6
5
4
3
2
1
0
EBR2
EB15 EB14 EB13 EB12 EB11 EB10 EB9
EB8
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. Bits 3 to 0 in
EBR2 are initialized to H'00 by a reset, in hardware standby mode and software standby mode,
when a low level is being input to the FWE pin, and when the SWE1 bit in FLMCR1 is not set
when a high level is being input to the FWE pin. Bits 7 to 4 are initialized to 0 when a low level is
input to the FWE pin, and when a high level is input to the FWE pin and the SWE2 bit in
FLMCR2 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other
blocks are erase-protected. Set only one bit in EBR2 and EBR1 together (setting more than one bit
will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled, a
read will return H'00, and writes are invalid.
The flash memory block configuration is shown in table 19.49.
Rev.6.00 Sep. 27, 2007 Page 866 of 1268
REJ09B0220-0600