D12320VF25IV Datasheet, PDF (1163/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
DTVECR—DTC Vector Register
H'FF37
DTC
Bit
:7
6
5
4
3
2
1
0
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
Initial value : 0
0
0
0
0
0
0
0
Read/Write : R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* _R/(W)* R/(W)*
Sets vector number for DTC software activation
DTC Software Activation Enable
0 DTC software activation is disabled
[Clearing conditions]
• When the DISEL bit is 0 and the specified number of transfers have
not ended
• When SWDTEND is requested to the CPU, then 0 is written to the
SWDTE bit
1 DTC software activation is enabled
[Holding conditions]
• When the DISEL bit is 1 and data transfer has ended
• When the specified number of transfers have ended
• During data transfer due to software activation
Note: * DTVEC6 to DTVEC 0 bits can be written to when SWDTE = 0.
Rev.6.00 Sep. 27, 2007 Page 1131 of 1268
REJ09B0220-0600