D12320VF25IV Datasheet, PDF (431/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 I/O Ports
Bit 0—Address 20 Enable (A20E): Enables or disables address output 20 (A₂₀). This bit is valid
in modes 4 to 6.
Bit 0
A20E
0
1
Description
DR is output when PA4DDR = 1
A20 is output when PA4DDR = 1
(Initial value)
System Control Register (SYSCR)
Bit
:
7
—
Initial value :
0
R/W
: R/W
6
5
4
3
2
1
0
—
INTM1 INTM0 NMIEG LWROD IRQPAS RAME
0
0
0
0
0
0
1
—
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7—Reserved: Only 0 should be written to this bit.
Bit 6—Reserved: This bit is always read as 0, and cannot be modified.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select either of
two interrupt control modes for the interrupt controller. For details of the interrupt control modes,
see section 5.4.1, Interrupt Control Modes and Interrupt Operation.
Bit 5
INTM1
0
1
Bit 4
INTM0
0
1
0
1
Interrupt
Control Mode
0
—
2
—
Description
Interrupt control by I bit
Setting prohibited
Interrupt control by bits I2 to I0
Setting prohibited
(Initial value)
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG
0
1
Description
Interrupt requested at falling edge of NMI input
Interrupt requested at rising edge of NMI input
(Initial value)
Rev.6.00 Sep. 27, 2007 Page 399 of 1268
REJ09B0220-0600