D12320VF25IV Datasheet, PDF (106/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
φ
Internal address bus
Read
access
Internal read signal
Internal data bus
Write
access
Internal write signal
Internal data bus
Bus cycle
T₁
Address
Read data
Write data
Figure 2.14 On-Chip Memory Access Cycle
Bus cycle
T₁
φ
Address bus
Unchanged
AS
High
RD
High
HWR, LWR
High
Data bus
High-impedance state
Figure 2.15 Pin States during On-Chip Memory Access
Rev.6.00 Sep. 27, 2007 Page 74 of 1268
REJ09B0220-0600