D12320VF25IV Datasheet, PDF (1193/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
SSR0—Serial Status Register 0
H'FF7C
SCI0
Bit
:
Initial value :
Read/Write :
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Multiprocessor Bit Transfer
0 Data with a 0 multiprocessor bit is transmitted
1 Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit
0 [Clearing condition]
When data with a 0 multiprocessor bit is received
1 [Setting condition]
When data with a 1 multiprocessor bit is received
Transmit End
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC*¹ or DTC is activated by a TXI interrupt
and writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a 1-byte
serial transmit character
Note: 1. The DMAC is not supported in the H8S/2321.
Parity Error
0 [Clearing condition]
When 0 is written to PER after reading PER = 1
1 [Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/E bit in SMR
Framing Error
0 [Clearing condition]
When 0 is written to FER after reading FER = 1
1 [Setting condition]
When the SCI checks the stop bit at the end of the receive
data when reception ends, and the stop bit is 0
Overrun Error
0 [Clearing condition]
When 0 is written to ORER after reading ORER = 1
1 [Setting condition]
When the next serial reception is completed while
RDRF = 1
Receive Data Register Full
0 [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DMAC*¹ or DTC is activated by an RXI interrupt and reads data from RDR
1 [Setting condition]
When serial reception ends normally and receive data is transferred
from RSR to RDR
Note: 1. The DMAC is not supported in the H8S/2321.
Transmit Data Register Empty
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC*¹ or DTC is activated by a TXI interrupt and writes data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Note: 1. The DMAC is not supported in the H8S/2321.
Note: * Can only be written with 0 for flag clearing.
Rev.6.00 Sep. 27, 2007 Page 1161 of 1268
REJ09B0220-0600